In many computer systems, the main memory controller generates a parity bit during a write cycle. This parity bit corresponds to a data word which is to be stored in the main memory of the system. The parity bit will indicate either that the data word has an even or odd number of bits with the value of "1". The parity bit and the data word are both provided to the main memory.
Conventional memory modules used for the main memory store both the data word and the parity bit. When the CPU requests that the data word be retrieved from memory, the memory module outputs both the stored data word and the stored parity bit.
In response to receiving the retrieved data word, the memory controller generates another parity bit and compares this parity bit with the original parity bit retrieved from memory. If the two parity bits do not match, the retrieved data word is different from the originally generated data word. This indicates that the retrieved data word was corrupted during storage or transmission. The system will then shut down and require the user to reset it.
One problem associated with these conventional memory modules is that they are no longer cost effective. Recent advances in the electronics industry have made memory products extremely reliable. As a result, differences in the compared parity bits occur very seldom. Thus, the advantage obtained from having additional memory in the memory module for storing the parity bits is no longer outweighed by the high cost of the additional memory.
Another problem associated with this approach is that the parity bits only indicate whether a data word has an even or an odd number of bits with the value "1". Thus, the retrieved data word can have two bits different than the originally generated data word but the compared parity bits will be the same. This effectively renders the additional memory for storing the parity bits useless. Thus, it makes it desirable to eliminate or bypass the addition of such memory.